DXGKARG_SIGNALMONITOREDFENCE - NtDoc
Native API online documentation, based on the System Informer
(formerly Process Hacker) phnt
headers
// d3dkmddi.h
typedef struct _DXGKARG_SIGNALMONITOREDFENCE {
DXGK_KERNEL_SUBMISSION_TYPE KernelSubmissionType;
VOID *pDmaBuffer;
D3DGPU_VIRTUAL_ADDRESS DmaBufferGpuVirtualAddress;
UINT DmaSize;
VOID *pDmaBufferPrivateData;
UINT DmaBufferPrivateDataSize;
UINT MultipassOffset;
D3DGPU_VIRTUAL_ADDRESS MonitoredFenceGpuVa;
UINT64 MonitoredFenceValue;
VOID *MonitoredFenceCpuVa;
HANDLE hHwQueue;
} DXGKARG_SIGNALMONITOREDFENCE;
View the official Windows Driver Kit DDI referenceNo description available.
Arguments used by the DXGKDDI_SIGNALMONITOREDFENCE callback function to add a GPU instruction to signal the paging monitored fence object to the DMA buffer.
KernelSubmissionTypeDescribes what type of kernel submission is being performed. This information can be used by the driver to choose the right synchronization class, and to ensure fence write instruction is generated in the format compatible with the buffer type being used.
pDmaBufferA pointer to the start of the DMA buffer, which is aligned on 4 KB.
DmaBufferGpuVirtualAddressA D3DGPU_VIRTUAL_ADDRESS data type that indicates the virtual address where the DMA buffer was paged in. If the physical address is zero, the DMA buffer is not correctly paged in.
DmaSizeThe size, in bytes, of the DMA buffer that pDmaBuffer points to.
pDmaBufferPrivateDataA pointer to a driver-resident private data structure that is used for generating the DMA buffer that pDmaBuffer points to.
DmaBufferPrivateDataSizeThe number of bytes that remain in the private data structure that pDmaBufferPrivateData points to for the current operation.
MultipassOffsetA value that specifies the progress of the rendering operation.
MonitoredFenceGpuVaGPU VA of the monitored fence value to be updated.
MonitoredFenceValueFence value to write from the DMA buffer being built.
MonitoredFenceCpuVaKernel mode CPU VA of the monitored fence value to be updated.
hHwQueueHandle to the hardware queue that the DMA buffer will be submitted to.